ST52T430 datasheet(24/88 Pages) STMICROELECTRONICS

24 / 88 page

ST52T430/E430

24/88

Figure 3.2 Eprom Programming Timing

The operations above are managed by using the

internal 4-bit EPROM Control Register. The

reading phase is executed with VPP= 5V±5%, while

the

verify/Margin

Mode

phase

needs

VPP=

12V

±5%. The Blank Check must be a reading

operation with VPP= 5V±5%.

Table 3.2 illustrates EPROM Control Register

codes used to identify the operation running.

3.1 EPROM Programming Phase Procedure

The Programming mode is selected by applying

12V

±5% voltage or 5V±5% voltage to the V

PP pin

and setting the control signal as following:

RESET =Vss

TEST =Vss

If the VPP voltage is 5V±5% only reading may be

performed.

RST_ADD, INC_ADD, RST_CONF, INC_CONF

and PHASE are the control signals used during the

Programming Mode.

PHASE, RST_CONF and RST_ADD signals are

active on level, the others are active on rising

edge.

Table 3.2 EPROM Control Register

OPERATION

Stand By

Memory Reading/Verify

Memory Unlock and

Lock Status Reading

Memory Writing

Memory Lock

ID CODE Writing

Memory Lock Status

Reading/Verify

ID CODE Reading/

Verify

MEMORY UNLOCK

MEMORY WRITING

LOCATION ADDRESS =1

DATA

MEMORY VERIFY

MARGIN MODE

DATA

OUT

VALID

DATA

VALID

DATA

VALID

DATA

OUT

DATA

OUT

100nS

µS

PA(0:7)

RST_ADD

RST_CONF

INC_ADD

INC_CONF

PHASE

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