ST52T430 datasheet(66/88 Pages) STMICROELECTRONICS

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ST52T430/E430

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A frame error can occur if the parity check hasn’t

been successfully achieved or if the STOP bit

hasn’t been detected.

the

Recovery

Buffer

Block

receives

consecutive bits at logic level 0, a break error

occurs and an interrupt routine request starts.

SCDR_RX Block

It is a finite state machine synchronized with the

clock master signal, CKM.

The SCDR_RX block waits for the signal of

complete reception from the Recovery Buffer, in

order to load the word received. Moreover, the

SCDR_RX block loads the values of FRERR and

NSERR flag bits (Input Register 19), and sets the

RXF flag to 1.

Data is transferred to RAM and the RXF flag is

reset to 0 by using the LDRI instruction in order to

indicate that the SCDR_RX block is empty.

If new data arrives before the previous one has

been transferred to Register File, an overrun error

occurs and OVERR flag of Input Register 19 is set

to 1.

11.2 SCI Transmitter Block

The SCI Transmitter Block consists of the following

blocks:

SCDR_TX

and

SHIFT

synchronized, respectively, with the clock master

signal (CKM) and the CLOCK_TX.

The whole block receives the settings for the

following transmission modes (see Table 11.1)

through Configuration Register 20 (M bits):

8-bit word and a single stop signal

8-bit word plus a parity bit and a single stop

signal

8-bit word plus a double stop signal

9-bit word

In case of 9 bit frame transmission, the most

significative

bit

arrives

through

the

Configuration Register 20.

Instead, in an 8-bit transmission T8 is used to

configure SCI according to information contained

in M (see Table 11.1). In particular, it is used to

choose the polarity control (even or odds) in order

to implement the parity check.

After a RESET signal RST, the SCDR_TX block is

in IDLE state until it receives the enabling signal

TE=1, of Configuration Register 20.

Data is loaded on the peripheral register (OR 9) by

using the instruction LPPR or LDPE. If TE=1 the

data to be transmitted is transferred from DR_TX

block and flag of Input Register 19. TXEM is reset

to 0 in order to indicate that the SCDR_TX block is

full.

Table 11.2 Configuration Register 19 Setting

Bit

Name

Value

Description

Not used

ECKF

5 MHz

10 MHz

20 MHz

5 MHz

TXC

SCI End

Transmission

Interrupt Disabled

SCI End

Transmission

Interrupt Enabled

TDRE

SCI Transmission

Data Register Empty

Interrupt Disabled

SCI Transmission

Data Register Empty

Interrupt Enabled

BRK

SCI Break Error

Interrupt Disabled

SCI Break Error

Interrupt Enabled

OVR

SCI Overrun Error

Interrupt Disabled

SCI Overrun Error

Interrupt Enabled

RDRF

SCI Received Data

Disabled

SCI Received Data

Enabled

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