ST52T430 datasheet(30/88 Pages) STMICROELECTRONICS

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ST52T430/E430

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Figure 4.5 Interrupt Configuration Register 17 & 18

4.5 Interrupt Priority

Seven priority levels are available: level 6 has the

lowest priority, level 0 has the highest priority.

Level 6 is associated to the Main Program, levels 5

to 1 are programmable by means of the priority

registers

called

REG_CONF17

and

REG_CONF18 (see Figure 4.5 and Table 4.3);

whereas the higher level is related to the external

interrupt (INT_EXT).

PWM/Timers, UART and ADC are identified by a

three-bit Peripheral Codes (see Table 4.2); in order

to set the

i-th priority level the user must write the

peripheral label

i in the related INTi priority level.

i.e.

LDRC

10,

193

//(load

the

value

193=’11000001’ in the RAM Register 10)

LDRC

11,

168

//(load

the

value

168=’10101000’ in the RAM Register 11)

LDCR

17,

set

the

REG_CONF17=

‘11000001’

LDCR

18,

set

the

REG_CONF18=

‘10101000’

The following priority levels are defined:

Level 1: INT_PWM/TIMER0 (PWM/TIMER 0

Code: 001)

Level 2: INT_ADC (ADC Code: 000)

Level 3: Int_PWM/Timer2 (PWM/TIMER 2

Code: 011)

Level 4: INT_UART (UART Code: 100)

Level 5: INT_PWM/TIMER1 (PWM/TIMER 1

Code: 010)

Table 4.3 Conf. Register 17 & 18 Description

Bit

Name

Value

Level

0, 1,2

INT1

Periphera

l Code

High

3, 4,5

INT2

Periphera

l Code

Medium-High

6,7,8

INT3

Periphera

l Code

Medium-Low

9,10,11

INT4

Periphera

l Code

Low

12,13,1

INT5

Periphera

l Code

Very Low

INT 1

Not Used

INT 2

REG_CONF17

Interrupts Priority

D10

D11

D12

D13

D14

D15

REG_CONF18

INT 3

INT 5

INT 4

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