ST52T430 datasheet(20/88 Pages) STMICROELECTRONICS

20 / 88 page

ST52T430/E430

20/88

2.4 Arithmetic Logic Unit

The 8-bit Arithmetic Logic Unit (ALU) allows the

performance of arithmetic calculations and logic

instructions, which can be divided into 5 groups:

Load, Arithmetic, Jump, Interrupts and Program

Control

instructions

(refer

the

ST52x430

Assembler Set for further details).

The

computational

time

required

for

each

instruction consists of one clock pulse for each

Cycle plus 3 clock pulses for the decoding phase.

The

ALU

the

ST52x430

can

perform

multiplication

(MULT)

and

division

(DIV).

Multiplication is performed by using 8 bit operands

storing the result in 2 registers (16 bit values), see

Figure 2.5 and Figure 2.6.

WARNING: If the LSB of the multiplication

result is 0, the Zero flag is set although the

result is not 0.

Table 2.4 Output Registers

OR MNEMONIC NAME

PERIPHERAL REGISTER

ADDRESS

PORT_ A

PORT A OR

PORT_ B

PORT B OR

PORT_C

PORT C OR

PWM_0_COUNT

TIMER/PWM 0 COUNTER

PWM_0_RELOAD

TIMER/PWM 0 RELOAD REGISTER

PWM_1_COUNT

TIMER/PWM 1 COUNTER

PWM_1_RELOAD

TIMER/PWM 1 RELOAD REGISTER

PWM_ 2_ COUNT

TIMER/PWM 2 COUNTER

PWM_2_RELOAD

TIMER/PWM 2 RELOAD REGISTER

SCI_TX_DATA

SCI DATA REGISTER

Table 2.5 Load instructions

Load Instructions

Mnemonic

Instruction

Bytes

Cycles

LDCE

LDCE conf, EPROM

LDCR

LDCR conf, RAM

LDFR

LDFR FUZZY_i_RAM RAM

LDPE

LDPE per, EPROM

LDPE

LDPE per, (RAM)

LDPR

LDPR reg, RAM

LDRC

LDRC RAM, const

LDRE

LDRE RAMi, EPROMi

LDRE

LDRE (RAMi), (RAMj)

LDRI

LDRI RAM, inp_reg

LDRR

LDRR RAMi, RAMj

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