ST52T430 datasheet(67/88 Pages) STMICROELECTRONICS

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ST52T430/E430

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Figure 11.3 SCI Status Input Register

If the core supplies new data it can’t be loaded in

the SCDR_TX block until the current data hasn’t

been unloaded on the Shift Register block.

Therefore, data may be loaded in the SCDR_TX

Block only when TXEM is 1.

When the SHIFT REGISTER Block loads data to

be transmitted on an internal buffer, TXEND is

reset to 0 in order to indicate the beginning of a

new transmission. At the end of transmission

TXEND is set to 1, allowing to load new data

coming from SCDR_TX in the SHIFT REGISTER.

Note: TXEND = 1 does not mean SCDR_TX is

ready to receive new data. For this reason it is

better to utilize the TXEM signal in order to

synchronize the LDPR instruction to the SCI

TRANSMITTER block

If the ST52x430 core resets TE to 0, the

transmission is interrupted, but the SCI Transmitter

block completes the transmission in progress

before reset.

Warning:

after the stop bit in SCI transmission an

idle time is present before the next start bit. This

time is equal to the duration of a bit transmission.

11.3 Baud Rate Generator Block

The Baud Rate Generator Block performs the

division of the clock master signal (CKM), in a set

of synchronism frequencies for the serial bit

reception/transmission on the external line.

Table 11.1 illustrates the set of frequencies

selected

means

BRSL

(Configuration

Reception frequency (CLOCK_RX) is 16 times

higher than transmission frequency (CLOCK_TX).

The following example illustrates a simple way to

use SCI to receive and transmit data:

LDRC 1 155

LDCR 20 1

These instructions load value 155

on the Configuration Register 20

fixing the Baud Rate=9600, 8 bit

data, TE=1, RE=1; Parity; 1 stop bit.

LDRC 1 252

LDCR 19 4

SCI

Interrupts

enabled,

clock

frequency 20 MHz

LDRC 1 170

LDPR 9 1

Send data to transmission buffer

WAITI

LDRI 6 19

Save the SCI status register on the

RAM

LDRI 1 18

Save the received data on a RAM

D7 D6 D5 D4 D3 D2 D1 D0

SCI_ST

Input Register 19

TXEND

- END TRANSMISSION

TXEM

- TRANSMISSION DATA REGISTER EMPTY

- RECEIVED NINTH BIT

NSERR

- NOISE ERROR

NOT USED

OVERR - OVERRUN ERROR

RXF

- RECEIVE DATA REGISTER FULL

FRERR

- FRAME ERROR

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