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ST52T430 数据表(PDF) 54 Page - STMicroelectronics |
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ST52T430 数据表(HTML) 54 Page - STMicroelectronics |
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54 / 88 page  ST52T430/E430 54/88 Figure 10.5 Configuration Register 5 Table 10.1 Configuration Register 5 Description Bit Name Value Description 0 TIRST0 0 PWM/TIMER 0 Internal RESET 1 PWM/TIMER 0 Internal SET 1 TERST 0 External RESET on Level 1 External RESET on Edge 2 TISTR0 0 PWM/TIMER 0 Internal STOP 1 PWM/TIMER 0 Internal START 3 TESTR 0 External START on Level 1 External START on Edge 4 INTE0 00 TIMER0 Interrupt on TIMER Interrupt on TIMEROUT Falling Edge 01 TIMER0 Interrupt on TIMER0OUT Rising Edge 5 10 TIMER0 Interrupt on Both Edges of TIMER0OUT 11 - not used 6 INTSL0 0 TIMER0 Interrupt on Counter Stop 1 TIMER0 Interrupt on TIMER0OUT 7 T0MODE 0 TIMER MODE 1 PWM MODE D7 D6 D5 D4 D3 D2 D1 D0 TIRST0: Timer 0 Internal RESET TERST: Timer 0 External RESET on Edge/Level TISTR0: Timer 0 Internal START TESTR: Timer 0 External START on Edge/Level INTE0: Timer 0 Interrupt on TIMER0OUT Rising/Falling Edge INTSL0: Timer 0 Interrupt Source selection T0MODE: Timer 0 working mode REG_CONF 5 TIMER 0 |
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