ST52T430 datasheet(14/88 Pages) STMICROELECTRONICS

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ST52T430/E430

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2 INTERNAL ARCHITECTURE

ST52x430 is made up of the following blocks and

peripherals:

Control Unit (CU) and Data Processing Unit

(DPU)

ALU / Fuzzy Core

EPROM

256 Byte RAM

Clock Oscillator

Analog Multiplexer and A/D Converter

3 PWM / Timers

SCI

Digital I/O port

2.1 ST52x430 Operating Modes

ST52x430 works in two modes, Programming and

Working Modes, depending on the control signals

level RESET, TEST and VPP

The Operating modes are selected by setting the

control signal level as specified in the Control

Signals Setting table.

2.2 Control Unit and Data Processing Unit

The Control Unit (CU) formally includes five main

blocks. Each block decodes a set of instructions,

generating the appropriate control signals. The

main parts of the CU are illustrated in Figure 2.1.

The five different parts of the CU manage Loading,

Logic/Arithmetic, Jump, Control and the Fuzzy

instruction set.

The block called “Collector” manages the signals

deriving from the different parts of the CU, defining

the signals for the Data Processing Unit (DPU) and

the different peripherals of the microcontroller.

The block called “Arbiter” manages the different-

parts of the CU so that only one part of the system

is activated during working mode.

The CU structure is very flexible. It was designed

with the purpose of easily adapting the core of the

microcontroller to market needs. New instruction

sets or new peripherals can be easily included

without

changing

the

structure

the

microcontroller, maintaining code compatibility.

The CU reads the instructions stored on EPROM

(Fetch) and decodes them. According to the

instruction types, the arbiter activates one of the

main blocks of the CU. Afterwards, all the control

signals for the DPU are generated.

A set of 46 different arithmetic, fuzzy and logic

instructions is available. Each instruction requires

6 (fuzzy instructions) to 26 (DIVISION) clock

pulses to be performed.

The DPU receives, stores and sends instructions

deriving from EPROM, RAM or peripherals in order

to execute them.

2.2.1 Program Counter.

The Program Counter (PC) is a 13-bit register that

contains the address of the next memory location

to be processed by the core. This memory location

may be an opcode, operand, or an address of an

operand.

The 13-bit length allows direct addressing of a

maximum of 8,192 bytes in the program space.

After having read the current instruction address,

the PC value is incremented. The result of this

operation is shifted back into the PC.

The PC can be changed in the following ways:

JP (Jump)PC = Jump Address

InterruptPC = Interrupt Vector

RETIPC = Pop (stack)

RETPC = Pop (stack)

CALLPC = Subroutines address

ResetPC = Reset Vector

Normal InstructionPC = PC + 1

2.2.2 Flags.

The ST52x430 core includes a different set of

flags that correspond to 2 different modes: normal

mode and interrupt mode. Each set of flags con-

sists of a CARRY flag (C), ZERO flag (Z) and

SIGN flag (S).

One set (CN, ZN, SN) is used during normal

operation and one is used during interrupt mode

(CI, ZI, SI). Formally, the user has to manage

only one set of flags: C, Z and S.

Table 2.1 Control Signals Setting

Control

Signal

Pro-

gramming

Reset

Working

RESET

VSS

VDD

TEST

VSS

VPP

12 V

VSS

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