ADE7166 datasheet(110/148 Pages) AD

110 / 148 page

ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 110 of 148

8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into

TL1 each time it overflows.

Timer/Counter 1 Stopped.

Gate0

Timer 0 Gating Control.

Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit

is set.

Cleared by software to enable Timer 0 whenever the TR0 control bit is set.

C_T0

Timer 0 Timer or Counter Select Bit.

Set by software to the select counter operation (input from T0 pin).

Cleared by software to the select timer operation (input from internal system clock).

Timer 0 Mode Select Bits

Description

TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.

16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.

8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into

TL0 each time it overflows.

1-0

T0_M1,

T0_M0

TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only, controlled by Timer 1 control bits.

Table 98. Timer/Counter 0 and 1 Control SFR (TCON, 0x88)

Bit

Location

Bit

Addr.

Bit

Name

Default

Value

Description

0x8F

TF1

Timer 1 Overflow Flag.

Set by hardware on a Timer/Counter 1 overflow.

Cleared by hardware when the program counter (PC) vectors to the interrupt service

routine.

0x8E

TR1

Timer 1 Run Control Bit.

Set by the user to turn on Timer/Counter 1.

Cleared by the user to turn off Timer/Counter 1.

0x8D

TF0

Timer 0 Overflow Flag.

Set by hardware on a Timer/Counter 0 overflow.

Cleared by hardware when the PC vectors to the interrupt service routine.

0x8C

TR0

Timer 0 Run Control Bit.

Set by the user to turn on Timer/Counter 0.

Cleared by the user to turn off Timer/Counter 0.

0x8B

IE11

External Interrupt 1 (INT1) Flag.

Set by hardware by a falling edge or by a zero level applied to the external interrupt pin,

INT1, depending on the state of Bit IT1.

Cleared by hardware when the PC vectors to the interrupt service routine only if the

interrupt was transition-activated. If level-activated, the external requesting source controls

the request flag rather than the on-chip hardware.

0x8A

IT11

External Interrupt 1 (IE1) Trigger Type.

Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.

Cleared by software to specify level-sensitive detection, that is, zero level.

0x89

IE01

External Interrupt 0 (INT0) Flag.

Set by hardware by a falling edge or by a zero level being applied to the external interrupt

pin, INT0, depending on the statue of Bit IT0.

Cleared by hardware when the PC vectors to the interrupt service routine only if the

interrupt was transition-activated. If level-activated, the external requesting source controls

the request flag rather than the on-chip hardware.

0x88

IT01

External Interrupt 0 (IE0) Trigger Type.

Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.

Cleared by software to specify level-sensitive detection, that is, zero level.

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