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ADE7166 数据表(PDF) 111 Page - Analog Devices |
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ADE7166 数据表(HTML) 111 Page - Analog Devices |
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111 / 148 page  Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 111 of 148 2 These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external INT0 and INT1 interrupt pins. Table 99. Timer/Counter 2 Control SFR (T2CON, 0xC8) Bit Location Bit Addr. Bit Name Default Value Description 7 0xCF TF2 0 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. 6 0xCE EXF2 0 Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software. 5 0xCD RCLK 0 Receive Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by the user to enable Timer 1 overflow to be used for the receive clock. 4 0xCC TCLK 0 Transmit Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by the user to enable Timer 1 overflow to be used for the transmit clock. 3 0xCB EXEN2 0 Timer 2 External Enable Flag. Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by the user for Timer 2 to ignore events at T2EX. 2 0xCA TR2 0 Timer 2 Start/Stop Control Bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. 1 0xC9 CNT2 0 Timer 2 Timer or Counter Function Select Bit. Set by the user to select the counter function (input from external T2 pin). Cleared by the user to select the timer function (input from on-chip core clock). 0 0xC8 CAP2 0 Timer 2 Capture/Reload Select Bit. Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Table 100. Timer 0 High byte SFR (TH0, 0x8C) Bit Location Bit Mnemonic Default Value Description 7-0 TH0 0 Timer 0 Data high byte Table 101. Timer 0 Low byte SFR (TL0, 0x8A) Bit Location Bit Mnemonic Default Value Description 7-0 TL0 0 Timer 0 Data high byte Table 102. Timer 1 High byte SFR (TH1, 0x8D) Bit Location Bit Mnemonic Default Value Description 7-0 TH1 0 Timer 1 Data high byte Table 103. Timer 1 Low byte SFR (TL1, 0x8B) Bit Location Bit Mnemonic Default Value Description 7-0 TL1 0 Timer 1 Data high byte |
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