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ADE7166 数据表(PDF) 115 Page - Analog Devices |
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ADE7166 数据表(HTML) 115 Page - Analog Devices |
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115 / 148 page  Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 115 of 148 PLL The ADE75xx/ADE71xx is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy measurement clock is derived from the PLL clock and is maintained at 4.096/5 MHz, 819.2 kHz across all CD settings. The PLL is controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR (POWCON, 0xC5), a key is required to modify the register. First the Key SFR (KYREG, 0xC1) is written with the key, 0xA7, and then a new value is written to the Power Control SFR (POWCON, 0xC5). If the PLL loses lock, the MCU is reset and the PLLFAULT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the PLLACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLL_FLT flag. PLL SFR REGISTER LIST Power Control SFR (POWCON, 0xC5) Bit Location Bit Mnemonic Default Value Description 7 RESERVED X Reserved 6 METER_OFF 0 Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0 5 RESERVED 0 Reserved 4 COREOFF 0 Set this bit to shut down the core if in the PSM1 operating mode. 3 RESERVED Reserved Controls the core clock frequency, Fcore. Fcore=4.096MHz/2CD CD[2:0] Fcore (MHz) 0 0 0 4.096 0 0 1 2.048 0 1 0 1.024 0 1 1 0.512 1 0 0 0.256 1 0 1 0.128 1 1 0 0.064 2-0 CD[2:0] 010 1 1 1 0.032 Table 109.Key SFR (KYREG, 0xC1) Bit Location Bit Mnemonic Default Value Description 7-0 KYREG 0 Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping register to unlock it. Peripheral Configuration SFR (PERIPH, 0xF4) Bit Location Bit Mnemonic Default Value Description 7 RXFLAG 0 If set, indicates that a RX Edge event triggered wakeup from PSM2 Indicates the power supply that is connected internally to VSW. 0 VSW=VBAT 6 VSWSOURCE 1 1 VSW=VDD 5 VDD_OK 0 If set, indicates that VDD power supply is ok for operation |
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