ADE7166 datasheet(118/148 Pages) AD

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ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 118 of 148

TEMPCAL

0xF7

RTC temperature compensation

INTPR

0xFF

RTC Calibration output options

KYREG

0xC1

Key Register

Table 110. RTC Configuration SFR (TIMECON, 0xA1)

Bit

Location

Bit

Mnemonic

Default

Value

Description

Midnight Flag

MIDNIGHT

This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by

the user to indicate that the midnight event has been serviced. In twenty-

four hour mode, the midnight flag is raised once a day at midnight.

Twenty-four hour mode

256 Hour mode. The HOUR register will roll over from 255 to 0.

24 Hour mode. The HOUR register will roll over from 23 to 0.

TFH

Note: This bit is retained during a watchdog reset or an external reset. It is

reset after a power on reset (POR).

Interval Timer Timebase Selection

ITS[1:0]

Timebase

1/128 second

Second

Minute

5-4

ITS[1:0]

Hour

Interval Timer One-Time Alarm

The ALARM flag will be set after INTVAL counts and then another

interval count will start.

SIT

The ALARM flag will be set after one time interval.

Interval Timer Alarm Flag

ALARM

This bit is set when the configured time interval has elapsed. It can be

cleared by the user to indicate that the alarm event has been serviced.

Interval Timer Enable

The interval timer is disabled. The 8-bit interval timer counter is

reset.

ITEN

Set this bit to enable the interval timer. The RTCEN bit must also

be set to enable the interval timer.

RTC Enable. Also Temperature, Battery and Supply ADC Background

Strobe Enable

RTCEN

Note: The RTC is always enabled.

Table 111. Hundredths of a Second Counter SFR (HTHSEC, 0xA2)

Bit

Location

Bit

Mnemonic

Default

Value

Description

This counter updates every 1/128 second, referenced from the calibrated

32kHz clock. It overflows from 127 to 00, incrementing the seconds

counter, SEC.

7-0

HTHSEC

Note: This register is retained during a watchdog reset or an external reset.

It is reset after a power on reset (POR).

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