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ADE7166 数据表(PDF) 119 Page - Analog Devices |
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ADE7166 数据表(HTML) 119 Page - Analog Devices |
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119 / 148 page  Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 119 of 148 Table 112. Seconds Counter SFR (SEC, 0xA3) Bit Location Bit Mnemonic Default Value Description This counter updates every second, referenced from the calibrated 32kHz clock. It overflows from 59 to 00, incrementing the minutes counter, MIN. 7-0 SEC 0 Note: This register is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). Table 113. Minutes Counter SFR (MIN, 0xA4) Bit Location Bit Mnemonic Default Value Description This counter updates every minute, referenced from the calibrated 32kHz clock. It overflows from 59 to 00, incrementing the hours counter, HOUR. 7-0 MIN 0 Note: This register is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). Table 114. Hours Counter SFR (HOUR, 0xA5) Bit Location Bit Mnemonic Default Value Description This counter updates every hour, referenced from the calibrated 32kHz clock. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is clear, the HOUR SFR overflows from 255 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. 7-0 HOUR 0 Note: This register is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). Table 115. Alarm Interval SFR (INTVAL, 0xA6) Bit Location Bit Mnemonic Default Value Description 7-0 INTVAL 0 The interval timer counts according to the timebase established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a pending RTC interrupt is created. Note that the interval counter is 8-bits so it could count up to 255 seconds, for example. Table 116. RTC Nominal Compensation SFR (RTCCOMP, 0xF6) Bit Location Bit Mnemonic Default Value Description The RTCCOMP SFR holds the nominal RTC compensation value at 25 °C. 7-0 RTCCOMP 0 Note: This register is reset after a watchdog reset, an external reset or a power on reset (POR). Table 117. RTC Temperature Compensation SFR (TEMPCAL, 0xF7) Bit Location Bit Mnemonic Default Value Description 7-0 TEMPCAL 0 The TEMPCAL SFR is adjusted based on the temerature read in the TEMPADC to calibrate the RTC over temperature. This allows the external crystal shift to be compensated over temperature. |
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