ADE7166 datasheet(121/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 121 of 148

must be checked for overflow. This can be accomplished

through the following 8052 assembly code:

ReadAgain:

MOV

R0, HTHSEC

; using Bank 0

MOV

R1, SEC

MOV

R2, MIN

MOV

R3, HOUR

MOV

A, HTHSEC

CJNE

A, 00h, ReadAgain

; 00h is R0 in Bank 0

RTC MODES

The RTC can be configured in a 24 hour mode or a 256 hour

mode. A midnight event is generated when the RTC hour

counter rolls over from 23 to 0 or 255 to 0, depending on

whether the TFH bit is set in the RTC Configuration SFR

(TIMECON, 0xA1). The midnight event sets the MIDNIGHT

flag in the RTC Configuration SFR (TIMECON, 0xA1) and a

pending RTC interrupt is created. The RTC midnight event will

wake the 8052 MCU core if the MCU is asleep in PSM2 when

the midnight event occurs. To acknowledge the midnight event,

service the RTC interrupt.

In the 24 hour mode, the midnight event is generated once a

day, at midnight. The 24 hour mode is useful for updating a

software calendar to keep track of the current day. The 256 hour

mode will result in power savings during extended operation in

PSM2 because the MCU core will be awoken less frequently.

RTC INTERRUPTS

The RTC Midnight and Alarm Interrupts are enabled by setting

the ETI bit in the Interrupt Enable and Priority 2 SFR (IEIP2,

0xA9). When a midnight or alarm event occurs, a pending RTC

interrupt is generated. If the RTC interrupt is enabled, the

program will vector to the RTC interrupt address and the

pending interrupt will be cleared. If the RTC interrupt is

disabled, then the RTC interrupt will remain pending until the

RTC interrupt is enabled. Then the program will vector to the

RTC interrupt address.

The MIDNIGHT and ALARM flags are set when the midnight

and alarm events occur, respectively. The user should manage

these flags to keep track of which event caused an RTC

interrupt by servicing the event and clearing the appropriate

flag in the RTC ISR.

Note that if the ADE7100/7500 is awakened by an RTC event,

either the MIDNIGHT or ALARM, then the pending RTC

interrupt must be serviced before the ADE7100/7500 can go

back to sleep again. The ADE7100/7500 will keep waking up

until this interrupt has been serviced.

Interval Timer Alarm

The RTC can be used as an interval timer. When the interval

timer is enabled by setting the ITEN bit in the RTC

Configuration SFR (TIMECON, 0xA1), the interval timer clock

source selected by the ITS1 and ITS0 bits is passed through to

an 8-bit counter. This counter increments on every interval

timer clock pulse until the 8-bit counter is equal to the value in

the Alarm Interval SFR (INTVAL, 0xA6). Then an alarm event

is generated, setting the ALARM flag and creating a pending

RTC interrupt. If the SIT bit in the RTC Configuration SFR

(TIMECON, 0xA1) is clear then the 8-bit counter is cleared and

starts counting again. If the SIT bit is set then the 8-bit counter

is held in reset after the alarm occurs.

Take care when changing the interval timer timebase. The

recommended prodedure is as follows:

If the INTVAL SFR is going to be modified, write

this register first. Then wait for one 128Hz clock

cycle, to synchronize with the RTC, 64000 cycles

at a 4.096MHz instruction cycle clock.

Disable the interval timer by clearing the ITEN

bit in the TIMECON SFR. Then wait for one

128Hz clock cycle, to synchronize with the RTC,

64000 cycles at a 4.096MHz instruction cycle

clock.

Read the TIMECON SFR to ensure that the ITEN

bit is clear. If it is not, wait for another 128Hz

clock cycle.

Set the timebase bits, ITS[1:0] in the TIMECON

SFR to configure the interval. Wait for a 128Hz

clock cycle for this change to take effect.

The RTC alarm event will wake the 8052 MCU core if the MCU

is in PSM2 when the alarm event occurs.

RTC CALIBRATION

The RTC provides registers to calibrate the nominal external

crystal frequency and its variation over temperature. Up to

±248ppm frequency error can be calibrated out by the RTC

circuitry, which adds or subtracts pulses from the external

crystal signal.

The nominal crystal frequency should be calibrated with the

RTCCOMP register so that the clock going into the RTC is

precisely 32.768 kHz at 25°C. The RTC Temperature

Compensation SFR (TEMPCAL, 0xF7) is used to compensate

for the external crystal drift over temperature by adding or

subtracting additional pulses based on temperature.

The LSB of each RTC compensation register represents a

±2ppm, or 0.17s/day, frequency error. The RTC compensation

circuitry adds the RTC Temperature Compensation SFR

(TEMPCAL, 0xF7) and the RTC Nominal Compensation SFR

(RTCCOMP, 0xF6) to determine how much compensation is

required and the sum of these two registers is limited to

±248ppm, or 42.85s/day.

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