ADE7166 datasheet(133/148 Pages) AD

133 / 148 page

Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 133 of 148

important, therefore, that CPHA and CPOL are configured the

same for the master and slave devices.

SS (Slave Select Pin)

In SPI slave mode, a transfer is initiated by the assertion of SS

low. The SPI port will then transmit and receive 8-bit data until

the data is concluded by deassertion of SS. In slave mode, SS is

always an input.

In SPI master mode, the SS can be used to control data transfer

to a slave device. In the automatic slave select control mode, the

SS is asserted low to select the slave device and then raised to

deselect the slave device after the transfer is complete.

Automatic slave select control is enabled by setting the

AUTO_SS bit in the SPI Configuration Register SFR (SPIMOD1,

0xE8)

In a multi-master system, the SS can be configured as an input

so that the SPI peripheral can operate as a slave in some

situations and as a master in other situations. In this case, the

slave selects for the slaves controlled by this SPI peripheral

should be generated with general I/O pins.

SPI MASTER OPERATING MODES

The double buffered receive and transmit registers can be used

to maximize the throughput of the SPI peripheral by

continuously streaming out data in master mode. The

continuous transmit mode is designed to use the full capacity

of the SPI. In this mode, the master will transmit and receive

data until the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)

is enabled by setting the SPICONT bit in the SPI Configuration

.The SPI peripheral also offers a

single byte read and a single byte write function.

In master mode, the type of transfer is handled automatically

depending on the configuration of bits 0 and 7 of the SPI

Configuration Register SFR (SPIMOD2, 0xE9)

. Table 133 shows

the sequence of events that should be performed for each

master operating mode. Based on the SS configuration, some of

these events will take place automatically.

Table 133. Procedures for using SPI as a Master

Mode

SPIMOD[7]

= SPICONT

bit

Description of operation

Step 1: Write to SPI2CTx SFR

Step 2: SS is asserted low and write routine is initiated

Step 3: SPITxIRQ Interrupt Flag is set when SPI2CTx register is empty

Step 4: SS is deasserted high

Single Byte

Write

Step 5: Write to SPI2CTx SFR to clear SPI2CTxIRQ Interrupt flag

Step 1: Write to SPI2CTx SFR

Step 2: SS is asserted low and write routine is initiated

Step 3: Wait for SPI2CTxIRQ Interrupt flag to write to SPI2CTx SFR. Transfer will

continue until the SPI2CTX register and transmit shift registers are empty.

Step 4: SPITxIRQ Interrupt Flag is set when SPI2CTx register is empty

Step 5: SS is deasserted high

Continuous

Step 6: Write to SPI2CTx SFR to clear SPITxIRQ Interrupt flag

Figure 82

shows the SPI output for certain automatic chip select

and continuous mode selections. Note that if the continuous

mode is not used, a short delay is inserted between transfers.

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