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ADE7166 数据表(PDF) 137 Page - Analog Devices |
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ADE7166 数据表(HTML) 137 Page - Analog Devices |
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137 / 148 page  Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 137 of 148 00 Fcore / 16 = 256kHz if Fcore = 4.096MHz 01 Fcore / 32 = 128kHz if Fcore = 4.096MHz 10 Fcore / 64 = 64Hz if Fcore = 4.096MHz 11 Fcore / 128= 32kHz if Fcore = 4.096MHz 4-0 0xEC – oxE8 I2CRCT[4:0] 0 Configures the length of the I2C received FIFO buffer. The I2C peripheral will stop when I2CRCT[4:0] + 1 bytes have been read or if an error has occured Table 136. I2C Slave Address SFR (I2CADR, 0xE9) Bit Location Bit Mnemonic Default Value Description 7-1 I2CSLVADR 0 Address of the I2C slave being adressed Writing to this register start the I2C transmission (Read or write) 0 I2CR_W 0 Command bit for Read or Write When this bit is set to logic one, a read command will be transmitted on the I2C bus. Data from slave in SPI2CRx SFR is expected after command byte When this bit is set to logic zero, a write command will be transmitted on the I2C bus. Data to slave is expected in SPI2CTx SFR Table 137. I2C Interrupt Status Register SFR (I2CSTAT, 0xEA) Bit Location Bit Mnemonic Default Value Description 7 I2CBUSY 0 This bit is set to logic one when the I2C interface is used. When this bit is set by user code, the Tx FIFO is emptied 6 I2CNOACK 0 I2C no acknlowledgement transmit interrupt This bit is set to logic one when the slave device did not send an acknlowledgement. The I2C communication is stopped after this event. Write a zero to this bit to clear it. 5 I2CRxIRQ 0 I2C receive interrupt This bit is set to logic one when the receive FIFO is not empty Write a zero to this bit to clear it. 4 I2CTxIRQ 0 I2C transmit interrupt This bit is set to logic one when the transmit FIFO is empty Write a zero to this bit to clear it. 3-2 I2CFIFOSTAT[1:0] 0 Status bit for 3 or 4 bytes deep I2C FIFO. The FIFO monitored in these 2 bits is the one currently used in I2C communication (Receive or Transmit) as only one of them is active at a time [1:0] 00 FIFO empty 01 Reserved 10 FIFO Half full 11 FIFO Full 1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a zero to this bit to clear it. 0 I2CTxWR_ERR 0 Set when write was attempted when I2C transmit FIFO was full. Write a zero to this bit to clear it. An I2C interrupt occurs * Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use the ADE7XXX in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. READ AND WRITE OPERATIONS |
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