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M32C/86 数据表(PDF) 136 Page - Renesas Technology Corp |
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M32C/86 数据表(HTML) 136 Page - Renesas Technology Corp |
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136 / 505 page ![]() Page 113 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 11. Interrupts ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Timer B2 Timer B0 Timer A0 Timer A1 Timer B1 UART1 Reception/ACK UART0 Reception/ACK A/D0 UART1 Transmission/NACK UART0 Transmission/NACK Key Input Interrupt IPL I Flag Watchdog Timer, Oscillation Stop Detection, Low Voltage Detection DMAC II NMI Interrupt request acknowledged (to CPU) Level 0 (Initial Value) Each Interrupt Priority Level Low Peripheral Function Interrupt Priority (if priority levels are the same) UART2 Reception/ACK Address Match Timer B4 Timer B3 DMA0 DMA1 DMA2 DMA3 Timer A2 Timer A3 Timer A4 UART2 Transmission/NACK UART3 Reception/ACK UART3 Transmission/NACK UART4 Reception/ACK UART4 Transmission/NACK Bus Conflict/Start, Stop Condition (UART0, UART3) Bus Conflict/Start, Stop Condition (UART1, UART4) RLVL2 to RLVL0 Bits Interrupt request priority detection results output (to the clock generation circuit) Bus Conflict/Start, Stop Condition(UART2) Intelligent I/O Interrupt 2 Intelligent I/O Interrupt 3 Intelligent I/O Interrupt 4 Intelligent I/O Interrupt 8 Intelligent I/O Interrupt 9 /CAN Interrupt 0 Intelligent I/O Interrupt 10 /CAN Interrupt 1 CAN Interrupt 2 INT3 INT5 INT4 INT1 INT2 INT0 Timer B5 Each Interrupt Priority Level Intelligent I/O Interrupt 0 /CAN Interrupt 3 Intelligent I/O Interrupt 1 /CAN Interrupt 4 CAN interrupt 5 NOTES: 1. Low voltage detection interrupt cannot be used in M32C/86T. (1) High Figure 11.9 Interrupt Priority Level Select Circuit |
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