M32CSLASH86 datasheet(137/505 Pages) RENESAS

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Page 114

11. Interrupts

)

(

External Interrupt Request Source Select Register

Symbol

Address

After Reset

IFSR

031F16

0016

INT0 Interrupt Polarity

Select Bit(1)

INT1 Interrupt Polarity

Select Bit(1)

INT2 Interrupt Polarity

Select Bit(1)

INT3 Interrupt Polarity

Select Bit(1)

INT4 Interrupt Polarity

select bit(1)

INT5 Interrupt Polarity

Select Bit(1)

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

Bit Name

Bit

Symbol

Function

NOTES:

1. Set this bit to "0" to select a level-sensitive triggering.

When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).

UART1, UART4

Interrupt Source

Select Bit

UART0, UART3

Interrupt Source

Select Bit

0 : One edge

1 : Both edges

IFSR3

IFSR4

IFSR5

IFSR6

IFSR0

IFSR2

IFSR1

IFSR7

0 : UART3 bus conflict, start condition

detect, stop condition detect

1 : UART0 bus conflict, start condition

detect, stop condition detect

0 : UART4 bus conflict, start condition

detect, stop condition detect

1 : UART1 bus conflict, start condition

detect, stop condition detect

______

11.7 INT Interrupt

______

External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge

sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an inter-

rupt at an applied signal level. The POL bit in the INTiIC register determines the polarity.

For edge sensitive, when the IFSRi bit in the IFSR register is set to "1", an interrupt occurs on both rising

and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding

_______

For level sensitive, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set

_______

in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains unchanged even if the INTi

_______

pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when the IR bit is

written to "0" by program.

Figure 11.10 shows the IFSR register.

Figure 11.10 IFSR Register

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