M32CSLASH86 datasheet(144/505 Pages) RENESAS

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12. Watchdog Timer

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12. Watchdog Timer

The watchdog timer monitors the program executions and detects defective program. It allows the micro-

computer to trigger a reset or to generate an interrupt if the program error occurs. The watchdog timer

contains a 15-bit counter, which is decremented by the CPU clock that the prescaler divides. The CM06 bit

in the CM0 register determines whether a watchdog timer interrupt request or reset is generated if the

watchdog timer underflows. The CM06 bit can only be set to "1" (reset). Once the CM06 bit is set to "1", it

cannot be changed to "0" ( watchdog timer interrupt) by program. The CM06 bit is set to "0" only after reset.

When the main clock, on-chip oscillator clock, or PLL clock runs as the CPU clock, the WDC7 bit in the

WDC register determine whether the prescaler divides the clock by 16 or by 128. When the sub clock runs

as the CPU clock, the prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer

cycle is calculated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.

When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock,

Watchdog timer cycle =

When the sub clock is selected as the CPU clock,

Watchdog timer cycle =

For example, if the CPU clock frequency is 30MHz and the prescaler divides it by 16, the watchdog timer

cycle is approximately 17.5 ms.

The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is

generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler

stop after reset. They begin counting when the WDTS register is set.

The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting

from the value held when the mode or state is exited.

Figure 12.1 shows a block diagram of the watchdog timer. Figure 12.2 shows registers associated with the

watchdog timer.

Divide-by-16 or -128 prescaler x counter value of watchdog timer (32768)

CPU clock

Divide-by-2 prescaler x counter value of watchdog timer (32768)

CPU clock

Watchdog Timer

Interrupt Request

Write to WDTS Register

Watchdog Timer

Set to

7FFF16

1/128

1/16

CM07 = 0

WDC7 = 1

CM07 = 0

WDC7 = 0

CM07 = 1

1/2

Prescaler

HOLD Signal

Reset

CM06 = 0

CM06 = 1

CPU Clock

CM06, CM07 : Bits in the CM0 Register

WDC7 : Bit in the WDC Register

PM22 : Bit in the PM2 Register

PM22 = 0

PM22 = 1

On-chip Oscillator Clock

Internal Reset Signal

Figure 12.1 Watchdog Timer Block Diagram

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