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H8/3028F 数据表(PDF) 387 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 387 Page - Renesas Technology Corp |
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387 / 923 page  Rev. 2.00, 09/03, page 357 of 890 9.5 Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR). The compare match signal is generated in the last state in which the values match (when 16TCNT is updated from the matching count to the next count). Therefore, when 16TCNT matches a general register, the compare match signal is not generated until the next 16TCNT clock input. Figure 9.33 shows the timing of the setting of IMFA and IMFB. φ 16TCNT GR IMF IMI 16TCNT input clock Compare match signal N N + 1 N Figure 9.33 Timing of Setting of IMFA and IMFB by Compare Match |
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