H8SLASH3028F datasheet(384/923 Pages) RENESAS

384 / 923 page

Rev. 2.00, 09/03, page 354 of 890

9.4.5

Phase Counting Mode

In phase counting mode the phase difference between two external clock inputs (at the TCLKA

and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly.

In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock

input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to

TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and

settings in TIOR2, TISRA, TISRB, TISRC, setting of STR2 bit in TSTR, GRA2, and GRB2 are

valid. The input capture and output compare functions can be used, and interrupts can be

generated.

Phase counting is available only in channel 2.

Sample Setup Procedure for Phase Counting Mode: Figure 9.29 shows a sample procedure for

setting up phase counting mode.

Phase counting mode

Select phase counting mode

Select flag setting condition

Start counter

Phase counting mode

Set the MDF bit in TMDR to 1 to select

phase counting mode.

Select the flag setting condition with

the FDIR bit in TMDR.

Set the STR2 bit to 1 in TSTR to start

the timer counter.

Figure 9.29 Setup Procedure for Phase Counting Mode (Example)

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