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H8/3028F 数据表(PDF) 528 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 528 Page - Renesas Technology Corp |
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528 / 923 page ![]() Rev. 2.00, 09/03, page 498 of 890 13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible. The transmitter and the receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in synchronous serial communication. Don't care One unit (character or frame) of transfer data MSB Bit 0 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 6 Bit 7 LSB Don't care Serial clock Serial data * * Note: * High except in continuous transmitting or receiving Figure 13.14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In each character, the serial data bits are transferred in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode the SCI receives data by synchronizing with the rise of the serial clock. Communication Format The data length is fixed at 8 bits. No parity bit or multiprocessor bit can be added. Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by means of the C/ A bit in SMR and the CKE1 and CKE0 bits in SCR. See table 13.9 for details of SCI clock source selection. When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. If receiving in single-character units is required, an external clock should be selected. |
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