H8SLASH3028F datasheet(557/923 Pages) RENESAS

557 / 923 page

Rev. 2.00, 09/03, page 527 of 890

14.3.6

Transmitting and Receiving Data

Initialization: Before transmitting or receiving data, the smart card interface must be initialized as

described below. Initialization is also necessary when switching from transmit mode to receive

mode, or vice versa.

1. Clear the TE and RE bits to 0 in the serial control register (SCR).

2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SSR).

3. Set the parity bit (O/

E) and baud rate generator select bits (CKS1 and CKS0) in the serial

mode register (SMR). Clear the C/

A, CHR, and MP bits to 0, and set the STOP and PE bits to

4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR).

When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI

pin functions and go to the high-impedance state.

5. Set a value corresponding to the desired bit rate in the bit rate register (BRR).

6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the

CKE0 bit is set to 1, the clock is output from the SCK pin.

7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE

bit and RE bit at the same time, except for self-diagnosis.

Transmitting Serial Data: As data transmission in smart card mode involves error signal

sampling and retransmission processing, the processing procedure is different from that for the

normal SCI. Figure 14.5 shows a sample transmission processing flowchart.

1. Perform smart card interface mode initialization as described in Initialization above.

2. Check that the FER/ERS error flag is cleared to 0 in SSR.

3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR.

4. Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation.

The TEND flag is cleared to 0.

5. To continue transmitting data, go back to step 2.

6. To end transmission, clear the TE bit to 0.

The above processing may include interrupt handling DMA transfer.

If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt

requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in

transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are

enabled, a transmit/receive-error interrupt (ERI) will be requested.

The timing of TEND flag setting depends on the GM bit in SMR (see figure 14.4).

If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be

transmitted automatically, including automatic retransmission.

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