H8SLASH3028F datasheet(554/923 Pages) RENESAS

554 / 923 page

Rev. 2.00, 09/03, page 524 of 890

Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to

0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention

type. To use the smart card interface, set the SMIF bit to 1.

The register settings and examples of starting character waveforms are shown below for two smart

cards, one following the direct convention and one the inverse convention.

1. Direct Convention (SDIR = SINV = O/

E = 0)

ZZZ

(Z)

State

With the direct convention type, the logic 0 level corresponds to state Z and the logic 1 level to

state A, and transfer is performed in LSB-first order. In the example above, the first character

data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.

2. Indirect Convention (SDIR = SINV = O/

E = 1)

AAAAAA

(Z)

State

With the indirect convention type, the logic 1 level corresponds to state Z and the logic 0 level

to state A, and transfer is performed in MSB-first order. In the example above, the first

character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity

rule designated for smart cards.

In the H8/3028 Group, inversion specified by the SINV bit applies only to the data bits, D7 to

D0. For parity bit inversion, the O/

E bit in SMR must be set to odd parity mode. This applies

to both transmission and reception.

H8/3028F 数据表(PDF) 554 Page - Renesas Technology Corp