H8SLASH3028F datasheet(550/923 Pages) RENESAS

550 / 923 page

Rev. 2.00, 09/03, page 520 of 890

Bits 6 to 0: These bits operate as in normal serial communication. For details see section 13.2.5,

Serial Mode Register (SMR).

14.2.4

Serial Control Register (SCR)

The function of SCR bits 1 and 0 is modified in smart card interface mode

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6,

Serial Control Register (SCR).

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and

enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to

specify a fixed high level or fixed low level for the clock output, in addition to the usual switching

between enabling and disabling of the clock output.

Bit 7

Bit 1

CKE1

Bit 0

CKE0

Description

Internal clock/SCK pin is I/O port

(Initial value)

Internal clock/SCK pin is clock output

Internal clock/SCK pin is fixed at low output

Internal clock/SCK pin is clock output

Internal clock/SCK pin is fixed at high output

Internal clock/SCK pin is clock output

14.3

Operation

14.3.1

Overview

The main features of the smart card interface are as follows.

• One frame consists of 8-bit data plus a parity bit.

• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of

one bit) is provided between the end of the parity bit and the start of the next frame.

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