H8SLASH3028F datasheet(549/923 Pages) RENESAS

549 / 923 page

Rev. 2.00, 09/03, page 519 of 890

Bit 2

TEND

Description

Transmission is in progress

[Clearing conditions]

• Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.

• The DMAC or DTC writes data in TDR.

End of transmission

[Setting conditions]

(Initial value)

• The chip is reset or enters standby mode.

• The TE bit and FER/ERS bit are both cleared to 0 in SCR.

• TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial

character is transmitted (normal transmission).

Note: etu (Elementary time unit: the time for transfer of one bit)

14.2.3

Serial Mode Register (SMR)

The function of SMR bit 7 is modified in smart card interface mode. This change also causes a

modification to the function of bits 1 and 0 in the serial control register (SCR).

R/W

CHR

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Bit 7—GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting

this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the

TEND flag that indicates completion of transmission, and the type of clock output used. The

details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in

the serial control register (SCR).

Bit 7

Description

Normal smart card interface mode operation

The TEND flag is set 12.5 etu after the beginning of the start bit.

Clock output on/off control only.

(Initial value)

GSM mode smart card interface mode operation

The TEND flag is set 11.0 etu after the beginning of the start bit.

Clock output on/off and fixed-high/fixed-low control.

Note: etu (Elementary time unit: the time for transfer of one bit)

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