H8SLASH3028F datasheet(551/923 Pages) RENESAS

551 / 923 page

Rev. 2.00, 09/03, page 521 of 890

• If a parity error is detected during reception, a low error signal level is output for a1 etu period

10.5 etu after the start bit.

• If an error signal is detected during transmission, the same data is transmitted automatically

after the elapse of 2 etu or longer.

• Only asynchronous communication is supported; there is no synchronous communication

function.

14.3.2

Pin Connections

Figure 14.2 shows a pin connection diagram for the smart card interface.

In communication with a smart card, since both transmission and reception are carried out on a

single data transmission line, the TxD pin and RxD pin should both be connected to this line. The

data transmission line should be pulled up to VCC with a resistor.

When the smart card uses the clock generated on the smart card interface, the SCK pin output is

input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is

unnecessary.

The reset signal should be output from one of the H8/3028 Group’s generic ports.

In addition to these pin connections, power and ground connections will normally also be

necessary.

TxD

RxD

SCK

Px (port)

H8/3028 Group

chip

VCC

I/O

Data line

Clock line

Reset line

CLK

RST

Card-processing device

Smart card

Figure 14.2 Smart Card Interface Connection Diagram

Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a

smart card.

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