H8SLASH3028F datasheet(567/923 Pages) RENESAS

567 / 923 page

Rev. 2.00, 09/03, page 537 of 890

D0 D1 D2 D3 D4 D5 D6 D7 Dp

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

(DE)

Ds D0 D1 D2 D3 D4

Frame n+1

Retransmitted frame

Frame n

RDRF

[1]

PER

[2]

[3]

[4]

Figure 14.12 Retransmission in SCI Receive Mode

• Retransmission when SCI is in Transmit Mode

Figure 14.13 illustrates retransmission when the SCI is in transmit mode.

6. If an error signal is sent back from the receiving device after transmission of one frame is

completed, the FER/ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state,

an ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity

bit sampling timing.

7. The TEND bit in SSR is not set for the frame for which the error signal was received.

8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.

9. If an error signal is not sent back from the receiving device, transmission of one frame,

including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in

SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is

enabled as a DMA transfer activation source, the next data can be written in TDR

automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to

D0 D1 D2 D3 D4 D5 D6 D7 Dp DE

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

(DE)

Ds D0 D1 D2 D3 D4

Frame n+1

Retransmitted frame

Frame n

TDRE

TEND

[6]

ERS

Transfer from TDR to TSR

[7]

[9]

[8]

Figure 14.13 Retransmission in SCI Transmit Mode

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