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H8/3028F 数据表(PDF) 574 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 574 Page - Renesas Technology Corp |
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574 / 923 page ![]() Rev. 2.00, 09/03, page 544 of 890 15.2.2 A/D Control/Status Register (ADCSR) Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 0 CH0 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W Note: * Only 0 can be written, to clear the flag. A/D end flag Indicates end of A/D conversion A/D interrupt enable Enables and disables A/D end interrupts A/D start Starts or stops A/D conversion Scan mode Selects single mode or scan mode Clock select Selects the A/D conversion time Channel select 2 to 0 These bits select analog input channels ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 ADF Description 0 [Clearing conditions] (Initial value) • Read ADF when ADF =1, then write 0 in ADF. • DMAC activated by ADI interrupt. 1 [Setting conditions] • Single mode: A/D conversion ends • Scan mode: A/D conversion ends in all selected channels |
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