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H8/3028F 数据表(PDF) 575 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 575 Page - Renesas Technology Corp |
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575 / 923 page ![]() Rev. 2.00, 09/03, page 545 of 890 Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE Description 0 A/D end interrupt request (ADI) is disabled (Initial value) 1 A/D end interrupt request (ADI) is enabled Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit timer compare match. Bit 5 ADST Description 0 A/D conversion is stopped (Initial value) 1 • Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. • Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode. Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN Description 0 Single mode (Initial value) 1 Scan mode Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3 CKS Description 0 Conversion time = 134 states (maximum) (Initial value) 1 Conversion time = 70 states (maximum) |
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