H8SLASH3028F datasheet(676/923 Pages) RENESAS

676 / 923 page

Rev. 2.00, 09/03, page 646 of 890

MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed

from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC.

20.7

System Clock Output Disabling Function

Output of the system clock (

φ) can be controlled by the PSTOP bit in MSTCRH. When the

PSTOP bit is set to 1, output of the system clock halts and the

φ pin is placed in the high-

impedance state. Figure 20.3 shows the timing of the stopping and starting of system clock output.

When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20.4 indicates

the state of the

φ pin in various operating states.

(PSTOP = 1)

(PSTOP = 0)

MSTCRH write cycle

High impedance

φ pin

Figure 20.3 Starting and Stopping of System Clock Output

Table 20.4

φφφφ Pin State in Various Operating States

Operating State

PSTOP = 0

PSTOP = 1

Hardware standby

High impedance

Software standby

Always high

High impedance

Sleep mode

System clock output

High impedance

Normal operation

System clock output

High impedance

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