H8SLASH3028F datasheet(674/923 Pages) RENESAS

674 / 923 page

Rev. 2.00, 09/03, page 644 of 890

20.5

Hardware Standby Mode

20.5.1

Transition to Hardware Standby Mode

Regardless of its current state, the chip enters hardware standby mode whenever the

STBY pin

goes low. Hardware standby mode reduces power consumption drastically by halting all functions

of the CPU, DMAC, DRAM interface, and on-chip supporting modules. All modules are reset

except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is

retained. I/O ports are placed in the high-impedance state.

Clear the RAME bit to 0 in SYSCR before

STBY goes low to retain on-chip RAM data.

The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby

mode.

20.5.2

Exit from Hardware Standby Mode

Hardware standby mode is exited by inputs at the

STBY and RES pins. While RES is low, when

STBY goes high, the clock oscillator starts running. RES should be held low long enough for the

clock oscillator to settle. When

RES goes high, reset exception handling begins, followed by a

transition to the program execution state.

20.5.3

Timing for Hardware Standby Mode

Figure 20.2 shows the timing relationships for hardware standby mode. To enter hardware standby

mode, first drive

RES low, then drive STBY low. To exit hardware standby mode, first drive

STBY high, wait for the clock to settle, then bring RES from low to high.

RES

STBY

Clock

oscillator

Oscillator

settling time

Reset

exception

handling

Figure 20.2 Hardware Standby Mode Timing

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