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H8/3028F 数据表(PDF) 671 Page - Renesas Technology Corp

部件名 H8/3028F
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
PDF  923 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8/3028F 数据表(HTML) 671 Page - Renesas Technology Corp

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Rev. 2.00, 09/03, page 641 of 890
20.4
Software Standby Mode
20.4.1
Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules
are reset and halted. As long as the specified voltage is supplied, however, CPU register contents
and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface* are also
held. When the WDT is used as a watchdog timer (WT/
IT = 1), the TME bit must be cleared to 0
before setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their
previous states.
20.4.2
Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI,
IRQ
0, IRQ1, or
IRQ
2 pin, or by input at the RES or STBY pin.
Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the
CPU.
Exit by
RES
RES
RES
RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied immediately to the entire chip. The
RES signal must be held low long enough for the
clock oscillator to stabilize. When
RES goes high, the CPU starts reset exception handling.
Exit by
STBY
STBY
STBY
STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.



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