H8SLASH3028F datasheet(667/923 Pages) RENESAS

667 / 923 page

Rev. 2.00, 09/03, page 637 of 890

20.2.2

Module Standby Control Register H (MSTCRH)

MSTCRH is an 8-bit readable/writable register that controls output of the system clock (

φ). It also

controls the module standby function, which places individual on-chip supporting modules in the

standby state. Module standby can be designated for the SCI0, SCI1, SCI2.

Bit

Initial value

Read/Write

PSTOP

R/W

—

MSTPH0

R/W

MSTPH2

R/W

MSTPH1

R/W

φ clock stop

Enables or disables

output of the system clock

Module standby H2 to 0

These bits select modules

to be placed in standby

Reserved bit

MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—

φφφφ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).

Bit 1

PSTOP

Description

System clock output is enabled

(Initial value)

System clock output is disabled

Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.

Bit 2—Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby.

Bit 2

MSTPH2

Description

SCI2 operates normally

(Initial value)

SCI2 is in standby state

Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.

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