H8SLASH3028F datasheet(665/923 Pages) RENESAS

665 / 923 page

Rev. 2.00, 09/03, page 635 of 890

20.2

The H8/3028 Group has a system control register (SYSCR) that controls the power-down state,

and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module

standby function. Table 20.2 summarizes these registers.

Table 20.2 Control Register

Address*

Name

Abbreviation

R/W

Initial Value

H'EE012

System control register

SYSCR

R/W

H'09

H'EE01C

Module standby control register H

MSTCRH

R/W

H'78

H'EE01D

Module standby control register L

MSTCRL

R/W

H'00

Note: * Lower 20 bits of the address in advanced mode.

20.2.1

System Control Register (SYSCR)

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

SSOE

R/W

Software standby

Enables transition to

software standby mode

RAM enable

Standby timer select 2 to 0

These bits select the

waiting time of the CPU

and peripheral functions

User bit enable

NMI edge select

Software standby

output port enable

SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1

(SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3,

System Control Register (SYSCR).

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