H8SLASH3028F datasheet(787/923 Pages) RENESAS

787 / 923 page

Rev. 2.00, 09/03, page 757 of 890

SYSCR—System Control Register

H'EE012

System control

Bit

Initial value

Read/Write

R/W

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

NMIEG

R/W

SSOE

R/W

RAME

NMI edge select

An interrupt is requested at the falling edge of NMI

An interrupt is requested at the rising edge of NMI

RAM enable

On-chip RAM is disabled

On-chip RAM is enabled

User bit enable

CCR bit 6 (UI) is used as an interrupt mask bit

CCR bit 6 (UI) is used as a user bit

Standby timer select 2 to 0

Bit 6

STS2

Waiting Time = 8,192 states

Waiting Time = 16,384 states

Waiting Time = 32,768 states

Waiting Time = 65,536 states

Waiting Time = 131,072 states

Waiting Time = 26,2144 states

Waiting Time = 1,024 states

Illegal setting

Bit 5

STS1

Bit 4

STS0

Standby Timer

Software standby

SLEEP instruction causes transition to sleep mode

SLEEP instruction causes transition to software standby mode

Software standby output port enable

In software standby mode,

all address bus and bus

control signals are high-

impedance

In software standby mode,

address bus retains output

state and bus control

signals are fixed high

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