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H8/3028F 数据表(PDF) 789 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 789 Page - Renesas Technology Corp |
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789 / 923 page  Rev. 2.00, 09/03, page 759 of 890 IER—IRQ Enable Register H'EE015 Interrupt Controller Bit Initial value Read/Write 0 R/W 7 — 0 R/W 6 — 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E IRQ5 to IRQ0 enable 0 1 IRQ5 to IRQ0 interrupts are disabled IRQ5 to IRQ0 interrupts are enabled ISR—IRQ Status Register H'EE016 Interrupt Controller Bit Initial value Read/Write 0 7 — — 0 6 — — 0 R/(W) * 5 IRQ5F 0 R/(W) * 4 IRQ4F 0 R/(W) * 3 IRQ3F 0 R/(W) * 2 IRQ2F 0 R/(W) * 1 IRQ1F 0 R/(W) * 0 IRQ0F IRQ5 to IRQ0 flags 0 Note: * Only 0 can be written, to clear the flag. Bits 5 to 0 IRQ5F to IRQ0F Setting and Clearing Conditions 1 (n = 5 to 0) [Clearing conditions] • Read IRQnF when IRQnF = 1, then write 0 in IRQnF. • IRQnSC = 0, IRQn input is high, and interrupt exception handling is being carried out. • IRQnSC = 1 and IRQn interrupt exception handling is being carried out. [Setting conditions] • IRQnSC = 0 and IRQn input is low. • IRQnSC = 1 and IRQn input changes from high to low. |
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