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H8/3028F 数据表(PDF) 792 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 792 Page - Renesas Technology Corp |
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792 / 923 page ![]() Rev. 2.00, 09/03, page 762 of 890 MSTCRH—Module Standby Control Register H H'EE01C System control 76 — 5 — 4 — 3 — 21 0 PSTOP MSTPH2 MSTPH1 MSTPH0 R/W R/W R/W R/W 01 — 1 — 1 — 1 — 00 0 Module standby H2 to H0 Selection bits for placing modules in standby state. Bit Initial value Read/Write Reserved bits φ clock stop Enables or disables φ clock output. MSTCRL—Module Standby Control Register L H'EE01D System control 76 — 5 43 2 1 — 0 MSTPL7 MSTPL2 MSTPL3 MSTPL4 MSTPL5 MSTPL0 R/W R/W R/W R/W R/W R/W R/W R/W 000 0 000 0 Module standby L7, L5 to L2, L0 Selection bits for placing modules in standby state. Reserved bits Bit Initial value Read/Write |
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