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H8/3028F 数据表(PDF) 827 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 827 Page - Renesas Technology Corp |
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827 / 923 page ![]() Rev. 2.00, 09/03, page 797 of 890 TISRC—Timer Interrupt Status Register C H'FFF66 16-bit timer (all channels) — 1 — 7 OVIE2 0 R/W 6 OVIE1 0 R/W 5 OVIE0 0 R/W 4 — 1 — 3 OVF2 0 R/(W) * 2 OVF1 0 R/(W) * 1 OVF0 0 R/(W) * 0 Bit: Initial value: Read/Write: Note: * Only 0 can be written, to clear the flag. Overflow flag 0 0 1 [Clearing condition] (Initial value) Read OVF0 when OVF0 = 1, then write 0 in OVF0. [Setting condition] TCNT0 overflowed from H'FFFF to H'0000. Overflow flag 1 0 1 [Clearing condition] (Initial value) Read OVF1 when OVF1 = 1, then write 0 in OVF1. [Setting condition] TCNT1 overflowed from H'FFFF to H'0000. Overflow flag 2 0 1 [Clearing condition] (Initial value) Read OVF2 when OVF2 = 1, then write 0 in OVF2. [Setting condition] TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF. Overflow interrupt enable 0 0 1 OVI0 interrupt requested by OVF0 flag is disabled (Initial value) OVI0 interrupt requested by OVF0 flag is enabled Overflow interrupt enable 1 0 1 OVI1 interrupt requested by OVF1 flag is disabled (Initial value) OVI1 interrupt requested by OVF1 flag is enabled Overflow interrupt enable 2 0 1 OVI2 interrupt requested by OVF2 flag is disabled (Initial value) OVI2 interrupt requested by OVF2 flag is enabled |
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