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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3028F 数据表(PDF) 828 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 828 Page - Renesas Technology Corp |
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828 / 923 page  Rev. 2.00, 09/03, page 798 of 890 TCR0—Timer Control Register H'FFF68 16-bit timer channel 0 Bit Initial value Read/Write 1 — 7 — 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 Timer prescaler 2 to 0 TCNT Clock Source Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Internal clock : φ (Initial value) Internal clock : φ/2 Internal clock : φ/4 Internal clock : φ/8 External clock A : TCLKA input External clock B : TCLKB input External clock C : TCLKC input External clock D : TCLKD input 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock edge 1 and 0 Counted Edges of External Clock Bit 4 CKEG1 Bit 3 CKEG0 Rising edges counted Falling edges counted Both edges counted 0 1 — 0 0 1 Counter clear 1 and 0 TCNT clear Sources Bit 6 CCLR1 Bit 5 CCLR0 TCNT is not cleared TCNT is cleared by GRA compare match or input capture TCNT is cleared by GRB compare match or input capture Synchronous clear : TCNT is cleared in synchronization with other synchronized timers 0 1 0 1 0 1 (Initial value) (Initial value) |
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