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H8/3028F 数据表(PDF) 108 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 108 Page - Renesas Technology Corp |
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108 / 923 page ![]() Rev. 2.00, 09/03, page 78 of 890 4.5 Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP–4 SP–3 SP–2 SP–1 SP (ER7) → SP (ER7) SP+1 SP+2 SP+3 SP+4 → SP–4 SP–3 SP–2 SP–1 SP (ER7) → SP (ER7) SP+1 SP+2 SP+3 SP+4 → Before exception handling Before exception handling After exception handling Stack area Stack area CCR CCR * PC PC CCR PC PC PC H L E H L After exception handling Even address Even address Pushed on stack Pushed on stack a. Normal mode b. Advanced mode Legend PCE: PCH: PCL: CCR: SP: Notes: PC indicates the address of the first instruction that will be executed after return. Registers must be saved in word or longword size at even addresses. * Ignored at return. Bits 23 to 16 of program counter (PC) Bits 15 to 8 of program counter (PC) Bits 7 to 0 of program counter (PC) Condition code register Stack pointer Figure 4.6 Stack after Completion of Exception Handling |
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