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H8/3028F 数据表(PDF) 111 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 111 Page - Renesas Technology Corp |
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111 / 923 page  Rev. 2.00, 09/03, page 81 of 890 Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). • Three-level masking by the I and UI bits in the CPU condition code register (CCR) • Seven external interrupt pins NMI has the highest priority and is always accepted*; either the rising or falling edge can be selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected independently. Note: * In the flash memory, NMI input is sometimes disabled. For details see 18.9, NMI Input Disable Conditions. |
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