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H8/3028F 数据表(PDF) 205 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 205 Page - Renesas Technology Corp |
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205 / 923 page ![]() Rev. 2.00, 09/03, page 175 of 890 H'00 φ RTCNT Address bus Internal write signal Counter clear signal T1 T2 T3 N RTCNT address Figure 6.39 Contention between RTCNT Write and Clear Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 6.40. M φ RTCNT T1 T2 T3 N Address bus RTCNT address Internal write signal RTCNT input clock Counter write data Figure 6.40 Contention between RTCNT Write and Increment |
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