H8SLASH3028F datasheet(212/923 Pages) RENESAS

212 / 923 page

Rev. 2.00, 09/03, page 182 of 890

Address bus

Simultaneous change of

HWR/LWR and CSn

Tc1 Tc2

Bus cycle A

(DRAM access cycle)

HWR/LWR

(

UCAS/LCAS)

Bus cycle B

CSn

Tc1 Tc2

Address bus

HWR/LWR

(

UCAS/LCAS)

CSn

Bus cycle A

(DRAM access cycle) Bus cycle B

(a) Idle cycle not inserted

(b) Idle cycle inserted

Figure 6.45 Example of Idle Cycle Operation (3) (

HWR

HWR/LWR

LWR

LWR Used as UCAS

UCAS

UCAS/LCAS

LCAS

LCAS)

Address bus

UCAS/LCAS

Tc1

Tc2

External read

DRAM space read

Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)

Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of

RD and the fall

(assertion) of

CSn may occur simultaneously. An example of the operation is shown in figure

6.47.

If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in

BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0

bit is cleared to 0, the

RD negation in the first read cycle and the CSn assertion in the following

bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,

it is possible that the low-level output of

RD in the preceding read cycle and the low-level output

CSn in the following bus cycle will overlap.

A setting whereby idle cycle insertion is not performed can be made only when

RD and CSn do

not change simultaneously, or when it does not matter if they do.

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