H8SLASH3028F datasheet(215/923 Pages) RENESAS

215 / 923 page

Rev. 2.00, 09/03, page 185 of 890

DMAC: When the DMAC receives an activation request, it requests the bus right from the bus

arbiter. If the DMAC is bus master and the DRAM interface or an external bus master requests

the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the

bus. The bus right is transferred at the following times.

The bus right is transferred when the DMAC finishes transferring one byte or one word. A

DMAC transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred

between the read cycle and the write cycle.

There is a priority order among the DMAC channels. For details see section 7.4.9, Multiple-

Channel Operation.

DRAM Interface: The DRAM interface requests the bus right from the bus arbiter when a refresh

cycle request is issued, and releases the bus at the end of the refresh cycle. For details see section

6.5, DRAM Interface.

External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an

external bus master. The external bus master has highest priority, and requests the bus right from

the bus arbiter y driving the

BREQ signal low. Once the external bus master acquires the bus, it

keeps the bus until the

BREQ signal goes high. While the bus is released to an external bus

master, the H8/3028 Group chip holds the address bus, data bus, bus control signals (

AS, RD,

HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds

the

BACK pin in the low output state.

The bus arbiter samples the

BREQ pin at the rise of the system clock (φ). If BREQ is low, the bus

is released to the external bus master at the appropriate opportunity. The

BREQ signal should be

held low until the

BACK signal goes low.

When the

BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the

bus-release cycle.

Figure 6.48 shows the timing when the bus right is requested by an external bus master during a

read cycle in a two-state access area. There is a minimum interval of three states from when the

BREQ signal goes low until the bus is released.

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