H8SLASH3028F datasheet(224/923 Pages) RENESAS

224 / 923 page

Rev. 2.00, 09/03, page 194 of 890

7.2

In short address mode, transfers can be carried out independently on channels A and B. Short

address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)

as indicated in table 7.4.

Table 7.4

Selection of Short and Full Address Modes

Channel

Bit 2

DTS2A

Bit 1

DTS1A

Description

DMAC channel 0 operates as one channel in full address mode

Other than above

DMAC channels 0A and 0B operate as two independent

channels in short address mode

DMAC channel 1 operates as one channel in full address mode

Other than above

DMAC channels 1A and 1B operate as two independent

channels in short address mode

7.2.1

Memory Address Registers (MAR)

A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or

destination address. The transfer direction is determined automatically from the activation source.

An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits

of MARR are reserved; they cannot be modified and are always read as 1.

Bit

Initial value

Read/Write

—

Source or destination address

—

R/W

Undetermined

R/W

MARR

MARE

MARH

MARL

An MAR functions as a source or destination address register depending on how the DMAC is

activated: as a destination address register if activation is by a receive-data-full interrupt from

serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt,

and as a source address register otherwise.

The MAR value is incremented or decremented each time one byte or word is transferred,

automatically updating the source or destination memory address. For details, see section 7.3.4,

Data Transfer Control Registers (DTCR).

The MARs are not initialized by a reset or in standby mode.

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