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H8/3028F 数据表(PDF) 263 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 263 Page - Renesas Technology Corp |
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263 / 923 page ![]() Rev. 2.00, 09/03, page 233 of 890 Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. DREQ RD HWR φ LWR , T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T1 CPU cycle DMAC cycle CPU cycle Minimum 4 states Next sampling point Address bus Figure 7.17 Timing of DMAC Activation by Low DREQ DREQ DREQ DREQ Level in Normal Mode |
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