H8SLASH3028F datasheet(265/923 Pages) RENESAS

265 / 923 page

Rev. 2.00, 09/03, page 235 of 890

7.4.9

Multiple-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.

Table 7.12 shows the complete priority order.

Table 7.12 Channel Priority Order

Short Address Mode

Full Address Mode

Priority

Channel 0A

Channel 0

High

Channel 0B

Channel 1A

Channel 1

Channel 1B

Low

If transfers are requested on two or more channels simultaneously, or if a transfer on one channel

is requested during a transfer on another channel, the DMAC operates as follows.

• When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it

starts a transfer on the highest-priority channel at that time.

• Once a transfer starts on one channel, requests to other channels are held pending until that

channel releases the bus.

• After each transfer in short address mode, and each externally-requested or cycle-steal transfer

in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if

there is a transfer request for another channel, the DMAC requests the bus again.

• After completion of a burst-mode transfer, or after transfer of one block in block transfer

mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a

higher-priority channel or a bus request from a higher-priority bus master, however, the

DMAC releases the bus after completing the transfer of the current byte or word. After

releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus

again.

Figure 7.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst

mode, and a transfer request for channel 0A is received while channel 1 is active.

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