H8SLASH3028F datasheet(271/923 Pages) RENESAS

部件名	H8/3028F

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	923 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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271 / 923 page

Rev. 2.00, 09/03, page 241 of 890

7.5

Interrupts

The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority.

Table 7.13 DMAC Interrupts

Description

Interrupt

Short Address Mode

Full Address Mode

Interrupt Priority

DEND0A

End of transfer on channel 0A

End of transfer on channel 0

High

DEND0B

End of transfer on channel 0B

—

DEND1A

End of transfer on channel 1A

End of transfer on channel 1

DEND1B

End of transfer on channel 1B

—

Low

Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control

The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B.

Figure 7.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and

DTIE = 1.

DTE

DTIE

DMA-end interrupt

Figure 7.25 DMA-End Interrupt Logic

The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The

DTME bit does not affect interrupt operations.

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