H8SLASH3028F datasheet(295/923 Pages) RENESAS

295 / 923 page

Rev. 2.00, 09/03, page 265 of 890

Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores output data

for port 5. When port 5 functions as an output port, the value of this register is output. When a bit

in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned. When a

bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin logic level is read.

Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write

—

R/W

Reserved bits

These bits store data

for port 5 pins

Port 5 data 3 to 0

P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Port 5 Input Pull-Up MOS Control Register (P5PCR): P5PCR is an 8-bit readable/writable

Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write

—

P5 PCR

R/W

P5 PCR

R/W

P5 PCR

R/W

P5 PCR

R/W

Reserved bits

These bits control input pull-up

transistors built into port 5

Port 5 input pull-up control 3 to 0

In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding

bit in P5PCR is set to 1, the input pull-up transistor is turned on.

P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting.

Table 8.9 summarizes the states of the input pull-ups in each mode.

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