H8SLASH3028F datasheet(305/923 Pages) RENESAS

305 / 923 page

Rev. 2.00, 09/03, page 275 of 890

8.9.2

Table 8.13 summarizes the registers of port 8.

Table 8.13 Port 8 Registers

Initial Value

Address*

Name

Abbreviation

R/W

Modes 1 to 4

Modes 5 to 7

H'EE007

Port 8 data direction

P8DDR

H'F0

H'E0

H'FFFD7

Port 8 data register

P8DR

R/W

H'E0

Note: * Lower 20 bits of the address in advanced mode.

Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select

input or output for each pin in port 8.

Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.

—

P8 DDR

Reserved bits

Port 8 data direction 4 to 0

These bits select input or

output for port 8 pins

Bit

Modes

1 to 4

Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

Modes 1 to 5 (Expanded Modes): When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to

3 output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports.

However, P81 can also be used as an output port, depending on the setting of bits DRAS2 to

DRAS0 in DRAM control register A (DRCRA). For details see section 6.5.2, DRAM Space and

RAS Output Pin Settings.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset P84 functions as

the

0 output, while CS1 to CS3 are input ports. In mode 5 (expanded mode with on-chip ROM

enabled), following a reset

0 to CS3 are all input ports.

When the refresh enable bit (RFSHE) in DRCRA is set to 1, P80 is used for RFSH output. When

RFSHE is cleared to 0, P80 becomes an input/output port according to the P8DDR setting. For

details see table 8.14.

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